The present invention relates generally to semiconductor wafers and their fabrication and, more particularly, to semiconductor wafers and their manufacture involving techniques for analyzing the wafers.
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages.
A by-product of such high-density and high functionality is an increased demand for products employing these microprocessors and devices for use in numerous applications. As the use of these devices has become more prevalent, the demand for faster operation and better reliability has increased. Such devices often require manufacturing processes that are highly complex and expensive.
As the manufacturing processes for semiconductor devices and integrated circuits increase in difficulty, methods for testing and debugging these devices become increasingly important. Not only is it important to ensure that individual chips are functional, it is also important to ensure that batches of chips perform consistently. In addition, the ability to detect a defective manufacturing process early is helpful for reducing the number of defective devices manufactured.
Various types of semiconductor devices and manufacturing systems require or benefit from one or more test, debug, or other analysis methods. Some structures are analyzed using several equipment types and/or methods, depending upon the type of information that is sought. In order to obtain different kinds of information, it is often desirable to test a particular semiconductor structure using multiple tools and/or analysis methods.
One type of analysis that can be performed is based upon hot carrier emissions, such as photons typically emitted from CMOS inverters during a logic state change. However, these emissions occur on time scales faster than 100 ps in modem integrated circuits. Therefore, a fast (greater than 100 ps) detector is necessary for recording these events. In addition, many devices from which the emissions are detected are often located in close proximity, necessitating a detector having high spatial resolution. For instance, current semiconductor technology permits the formation of transistors having a pitch on a micron or even sub-micron order.
There are various detectors and detection methods that are available for hot carrier emission analysis. For instance, a global detector allows parallel acquisition and fast timing resolution of the emissions, but has poor quantum efficiency. A single point avalanche photodiode (APD) detector has high quantum efficiency for fast acquisition but has slow time response. (Quantum efficiency is the ratio of hole-electron pairs or photoelectrons to the number of photons received by a photodetector. In general, the quantum efficiency can be as high as 80% for an APD and 25% for a PMT). A germanium (Ge), Gallium Arsenide (GaAs), or Indium Gallium Arsenide (InGaAs) APD can be added to speed acquisition, but each also generally exhibits a slow time response. For information regarding an example global detector, reference may be made to J. A. Kash and J. C. Tsang, Dynamic Internal Testing of CMOS Circuits using Hot Luminescence,xe2x80x9d IEEE ELECTRON DEVICE LETT., July 1997, vol. 18, at 330 and to U.S. Pat. No. 5,940,545 entitled xe2x80x9cNoninvasive Optical Method for Measuring Internal Switching and Other Dynamic Parameters of CMOS Circuits.xe2x80x9d For information regarding an example single point APD detector, reference may be made to U.S. Pat. No. 6,255,124, filed on Feb. 8, 1999.
Although there are various detectors available for acquiring hot carrier emission data, including the examples described above, it is desirable to have the ability to take advantage, in a single combined testing arrangement, of the particular qualities available from currently available detectors and methods. Such a combined testing arrangement would enhance the advancement of semiconductor technologies.
The present invention is directed to a method and system for analyzing a semiconductor device that provides the ability to take advantage of the positive aspects of more than one type of analysis tool. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to one example embodiment of the present invention, an integrated multi-dector system is adapted to analyze a semiconductor device under test (DUT) using more than one detector. The integrated system includes a microscope having an objective lens, a global acquisition sensor, a single-point acquisition sensor, and a navigation sensor used to align the microscope with the DUT. By integrating navigation, global acquisition, and single-point acquisition capabilities into a single system, a DUT can be efficiently analyzed using detectors having different capabilities, thereby enhancing the ability to analyze the DUT.
According to another example embodiment, the present invention is directed to a method for analyzing a semiconductor device under test (DUT). The DUT is navigated and a microscope having an objective lens is directed to a selected portion of the DUT for analysis. An image of the portion of the DUT is focused using the microscope. The focused image is used for integrated analysis via an integrated tool having the capabilities of acquiring both global emission data and single-point emission data from the DUT.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description which follow more particularly exemplify these embodiments.